This invention relates to a circuit architecture for processing multi-channell frames of broadband synchronous digital signals, in particular signals of the SONET/SDH standard, being of a type which comprises a receiving input portion and a transmitting output portion.
It is a universally recognized fact that the foreseeable future of planetary communications rests on broadband video signals.
Accordingly, an expanded application of such facilities as video telephone, video conferencing, video surveillance, color facsimile transmission, and cable television (CATV), calls for integrated circuit architectures which can handle broadband electric signals.
Moreover, the ever more widespread availability of communication and interconnection lines based on fiber optics demands integrated electronic circuits of suitable design and construction to handle broadband signals in an effective and efficient manner.
In this particular field transmission standards have been established, such as the standards known by the acronyms SONET (Synchronous Optical Network) or SDH (Synchronous Digital Hierarchy). These standards are set and controlled by CCITT, a US committee regulating synchronous transmissions based on optical communication.
These standards are useful to settle and organize the transmission protocols that enable information to be transmitted on communications networks, which are complex systems that interconnect communication components.
In particular, the standards considered in this specification expressly relate to the synchronous digital transmission and reception of digital signal frames. An exhaustive review of these problems is found in a text, Broadband Telecommunication Technology, Artech House, 1993, Chapter 3: xe2x80x9cSynchronous Digital Transmissionxe2x80x9d.
To better appreciate the aspects of the present invention, notice should be taken of that state-of-art frame processing involves:
A) On reception (RX):
1) signal pre-processing;
2) optional demultiplexing, i.e., a frame decomposition for extracting certain subchannels;
3) parallel processing of the individual channels forming the frame, but in such a way as to have each channel processed separately from the others;
B) On transmission (TX):
1) preparing in parallel the individual channels forming the frame;
2) multiplexing the various channels, if more than one are provided;
3) final processing of the whole frame.
Illustrated in block diagram form by the accompanying FIG. 1A is the structure of a conventional circuit architecture for processing a frame comprising a single channel. In this particular case, the multiplexing or demultiplexing steps obviously would not be required.
On the other hand, FIG. 1B shows, again in block diagram form, the structure of a conventional circuit architecture for processing a frame comprising N channels, with N=3 or N=4.
A further prior solution to the problem of processing multi-channel frames was made available to the general public in 1993 by TransSwitch Corporation, Shelton Conn., U.S.A., and described in a bulletin No. TXC-02201-MC, January 1993. FIG. 2 shows schematically a circuit architecture which operates in accordance with TransSwitch""s solution. Similar solution have been proposed by the Spanish Telephonic Company and by the company PCM Serra.
All these examples of applications currently available on the telecommunications market use N+1 components, that is, one component more than the number of channels in the frame.
All of the known solutions provide for the use of a single component to perform the pre-processing and demultiplexing functions on reception, as well as the multiplexing and final processing functions on transmission. In addition, they provide N components, identical with one another, to perform the function of processing in parallel the individual channels on reception, and preparing the individual independent channels on transmission.
Usually, the single component is a definitely smaller size than each of the N components. Its dimensions are smaller by a factor of one to five.
An embodiment of this invention provides a circuit architecture for processing broadband digital signal frames, particularly intended for the SONET/SDH standards, and for optionally decomposing them into subchannels. This architecture has such structural and functional characteristics as to ensure a substantial reduction in the number and dimensions of the circuit components employed, while also reducing costs and facilitating manufacture.
An embodiment of this invention provides a single component adapted to process single-channel frames, yet usable in a modular manner for a number N of times to process frames comprising N channels.
In one embodiment, the invention includes an input portion, an output portion, and a modular section adapted to process single channel frames. In another embodiment, N modular sections are coupled together and are able to decode frames containing N channels.
The features and advantages of the architecture according to this invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.